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Last created projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) Verilog Rijndael (AES) Implementation   Updated on: unknown   VLM: 1 This was a project for a college class, where I had to implement the Rijndael (AES) encryption/decryption algorithm. This code is provided mainly for educational reasons. The code is highly commented, and should be relatively easy for someone to ...     OpenRISC 1200 Fault Tolerant   Updated on: 02-Sep-2008   VLM: 175 a fault tolerant version of OpenRISC 1200 processor. it add modules that will protect Cache, Register file and Memory. the main goal of the project is to achive a fault-coverage of 95% with area-and-power overhead as low as possible suitable ...     FIR-Gen   Updated on: unknown   VLM: 27 This programm generates an synthesise able vhdl filter from Coefficients     FIR-Gen   Updated on: 28-Aug-2008   VLM: 274 This programm generates synthesis able vhdl code from filter coefficients. The programm is written in C++.     VHDL wavefile package   Updated on: 24-Aug-2008   VLM: 164 This short and simple package makes it easy to read and write wave files for signal processing in simulations. This is usefull if you want to check your simulation results with Octave. There are no restrictions about the numbers of channels or...     AES   Updated on: unknown   VLM: 36 I want to make a AES project, there is something problem, if you can help me ,give me a hand     68000 Compatible CPU core   Updated on: unknown   VLM: 45 A FPGA based CPU core compatible (timing as well as ISA) with MC68000. Although there are a couple of open source 68k cores are available on the net, but they lack design documentation and hence it is very difficult to comprehend them. I aim t...     Bluespec MD6   Updated on: unknown   VLM: 44 The first hardware implementation, a novel hashing algorithm by Ron Rivest. This algorithm is highly parallel. This code has been proven on the XUP platform, on which hashing speeds of 233 MB/s have been achieved.     Scalable Arbiter   Updated on: 08-Aug-2008   VLM: 392 A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines f...   Category :: Other Language :: Verilog Development status :: Beta   Standard SDIO Host Controller with Wishbone Interface   Updated on: 04-Aug-2008   VLM: 53 Standard SDIO Host Controller with Wishbone interface.