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Development status :: Production/Stable We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AES (Rijndael) IP Core   Updated on: 22-May-2007   VLM: 684 AES (Rijndael) IP Core. Complete with cipher and inverse cipher and key expansion block. Everything written in Verilog - high performace, small area.   Category :: Crypto core Language :: Verilog Development status :: Production/Stable   10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Aug-2008   VLM: 1515 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   128/192 AES   Updated on: 19-Sep-2005   VLM: 434 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   16 Bit Microcontroller   Updated on: 16-Apr-2006   VLM: 562 This is A 16 bit CPU, optimized for the execution of C programs. The CPU requires about 800 Xilinx slices, or about 1000 slices for a complete system on a chip with serial I/O and a few other I/O interfaces. The CPU comes with an assembler,...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   3DES (Triple DES) / DES (VHDL)   Updated on: 01-Dec-2006   VLM: 259 A VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.   Category :: Crypto core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   5x4Gbps CRC generator designed with standard cells   Updated on: 05-May-2004   VLM: 213 The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells ...   Category :: Arithmetic core Language :: VHDL License :: GPL Development status :: Production/Stable   68hc05   Updated on: 13-May-2007   VLM: 159 Rebuild of Motorola 68HC05 microcontroller only from a datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   68hc08   Updated on: 07-May-2007   VLM: 235 Rebuild of Motorola 68HC08 microcontroller only from datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   802.3an LDPC Decoder   Updated on: 20-Feb-2007   VLM: 380 LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm.   Category :: ECC core Language :: Verilog Development status :: Production/Stable   802.3an LDPC Encoder   Updated on: 20-Feb-2007   VLM: 318 A low-density parity-check encoder for the recently ratified 10GBASE-T standard (802.3an).   Category :: ECC core Language :: Verilog Development status :: Production/Stable   8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 184 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   8080 Compatible CPU   Updated on: 21-Nov-2006   VLM: 523 CPU8080 is a basic 8080 emulation in Verilog. It was completed as a project to learn Verilog, but it can be useful as a very small onchip controller CPU with very modest silicon area requirements. In addition, the 8080 has a long list of softw...   Category :: Microprocessor Language :: Verilog Phaze :: Design done Development status :: Production/Stable   8b10b Encoder/Decoder   Updated on: 05-Oct-2006   VLM: 467 This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limit...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 22-Jul-2008   VLM: 838 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   a VHDL 8254 Timer   Updated on: 24-Aug-2008   VLM: 740 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   A VHDL CAN Protocol Controller   Updated on: 03-Nov-2007   VLM: 505 A VHDL translation of the Verilog CAN Protocol Controller   Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Production/Stable   AC 97 Controller IP Core   Updated on: 22-May-2007   VLM: 414 This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   ACEX 1K50 board   Updated on: 11-Sep-2004   VLM: 197 A prototyping board with ACEX 1K50, 128 KB SRAM, 512 KB Flash, serial driver and wtachdog.   Category :: Prototype board License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   ae18   Updated on: 11-Oct-2007   VLM: 280 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 522 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AES core modules   Updated on: 15-May-2007   VLM: 432 AES modules in VHDL. This is base implementation of algorithm described in http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf   Category :: Crypto core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   AES128   Updated on: 28-Dec-2004   VLM: 405 Advanced Encryption Standard Cryptographic Core   Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   ahb system generator   Updated on: 02-Nov-2007   VLM: 278 It's a PERL/TK script to define and configure an AHB system. A configuration and matrix file is generated comprising arbiters, decoders and master and slave muxes. A complete system file is also generated with AHB simple masters and slaves inst...   Category :: SoC Language :: VHDL Phaze :: Design done Development status :: Production/Stable   AMI / HDB1 Line Codes   Updated on: 25-Nov-2007   VLM: 93 VHDL implementation of the AMI --- Alternate Mark Inverse --- and HDB1 --- High Density Bipolar of Order 1 line codes. For HDBn of higher order look at: http://www.opencores.org/projects/hdbn   Category :: Communication controller Language :: VHDL Development status :: Production/Stable   Aquarius   Updated on: 04-Jul-2004   VLM: 285 Aquarius is an IP core of pipelined RISC CPU, which is compatible with instruction set of SuperH-2.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   ASPIDA sync/async DLX Core   Updated on: 23-Sep-2005   VLM: 223 The ASPIDA (ASynchronous Processor Ip of the Dlx Architecture) project aims to demonstrate the industrial viability and IP Reuse potential of asynchronous parts by delivering a free, open-source, industrial-quality, asynchronous IP Processor Core...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   Automatic BAUD rate generator   Updated on: 21-Jan-2007   VLM: 194 This module allows for RS232 serial communications (UART) to automatically synthesize a BAUD rate to match incoming serial data, regardless of the FPGA clock rate. It works by measuring the speed of the incoming characters, and producing its own...   Category :: Communication controller Development status :: Production/Stable   AVR Core   Updated on: 27-Feb-2008   VLM: 2136 AVR core, UART, Timer/Counter and parallel ports   Category :: Microprocessor Development status :: Production/Stable   AX8 mcu   Updated on: 06-Mar-2007   VLM: 252 90S1200/2313 microcontroller core   Category :: Microprocessor Development status :: Production/Stable   Basic DES Crypto Core   Updated on: 15-Oct-2005   VLM: 209 Fast, small ECB mode DES encryption and decryption. Can be daisychained to implement TripleDES. Additional logic required for CFB, CBC, and other modes.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   Basic RSA Encryption Engine   Updated on: 15-Oct-2005   VLM: 249 A no-frills implementation of the RSA Public Key Encryption algorithm. The design is intended as an exercise in hardware design, and meets only two requirements: 1) It must work. 2) It must fit within a commercially available FPGA.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   baud generator   Updated on: 20-Dec-2007   VLM: 191 block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse. Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Param...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Binary to BCD conversions, with LED display driver   Updated on: 25-Oct-2005   VLM: 254 Modules for converting binary input to Binary Coded Decimal (BCD) output, and for converting Binary Coded Decimal input to binary output. Tested in hardware. Parameterized Verilog.   Category :: Arithmetic core Development status :: Production/Stable   Biquad IIR Filter Core   Updated on: 14-Oct-2001   VLM: 347 IIR filter with two poles and two zeros.   Category :: DSP core Development status :: Production/Stable   Bluespec 802.11a Transmitter   Updated on: 02-Jul-2008   VLM: 250 This Project is the implementation of a 80.211a Transmitter baseband block in BSV (Bluespec SystemVerilog).   Category :: Communication controller Language :: Other Development status :: Production/Stable   boundaries   Updated on: 07-Jul-2004   VLM: 137 A collection of useful multi-clock and clock-boundary designs.   Category :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable   CAN Protocol Controller   Updated on: 30-Apr-2008   VLM: 1591 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   CF Cordic   Updated on: 08-May-2008   VLM: 333 Confluence generated cordics.   Category :: Arithmetic core Development status :: Production/Stable   CF FFT   Updated on: 08-May-2008   VLM: 748 Confluence generated FFTs (Fast Fourier Transforms).   Category :: Arithmetic core Development status :: Production/Stable   CF FIR Filter   Updated on: 08-May-2008   VLM: 272 Confluence generated finite impulse response (FIR) filters.   Category :: DSP core Development status :: Production/Stable   CF Floating Point Multiplier   Updated on: 08-May-2008   VLM: 278 Confluence generated floating point multipliers.   Category :: Arithmetic core Development status :: Production/Stable   CF Interleaver   Updated on: 08-May-2008   VLM: 163 Confluence generated memory interleavers.   Category :: Memory core Development status :: Production/Stable   CF LDPC Decoder   Updated on: 08-May-2008   VLM: 227 Confluence generated low-density parity-check (LDPC) decoder.   Category :: ECC core Development status :: Production/Stable   CF Reconfigurable Computing Array   Updated on: 08-May-2008   VLM: 180 Confluence generated reconfigurable computing array.   Category :: Coprocessor Development status :: Production/Stable   CF State Space Processor   Updated on: 08-May-2008   VLM: 176 Confluence generated state space processor for multivariable linear systems.   Category :: Microprocessor Development status :: Production/Stable   ClaiRISC - runs 12bit opcode PIC family.   Updated on: 05-Aug-2008   VLM: 354 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Color Converter   Updated on: 26-Feb-2007   VLM: 342 Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...   Category :: Video controller Dependencies :: Other cores Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Complete SoC based on C-NIT processor   Updated on: 23-Feb-2004   VLM: 123 The goal is to develop a complete SoC based on C-NIT 16 bit CPU. Current implementation includes - C-NIT processor - SDRAM controller. - Cache controller. - LCD and 7 segment drivers. - Keyboard controller. - Glue logic. An assembler f...   Category :: SoC Development status :: Production/Stable   Configurable Hamming Generator   Updated on: 21-Aug-2007   VLM: 224 This program automatically generates Hamming encoder and decoder for a given word width. It also generates a testbench to evaluate the generate modules.   Category :: ECC core Language :: VHDL License :: GPL Development status :: Production/Stable   CORDIC core   Updated on: 14-Feb-2004   VLM: 981 The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Cpu Generator   Updated on: 03-Mar-2004   VLM: 442 CpuGen (TM) generates customizable RISC cpu cores. It allows direct customization of address/data/instruction bus size, interrupt handling, indirect addressing, data/instruction latency timings and custom instructions definition. It is targeted...   Category :: Microprocessor Language :: VHDL Development status :: Production/Stable   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 262 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development