By category :: Last updated :: Last created :: Most popular :: Best rated

Standard :: Wishbone compliant core We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 128/192 AES   Updated on: 19-Sep-2005   VLM: 434 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   16 Bit Microcontroller   Updated on: 16-Apr-2006   VLM: 562 This is A 16 bit CPU, optimized for the execution of C programs. The CPU requires about 800 Xilinx slices, or about 1000 slices for a complete system on a chip with serial I/O and a few other I/O interfaces. The CPU comes with an assembler,...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   8051 core   Updated on: 29-Jul-2008   VLM: 1681 The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 64K bytes of on-chip program memory.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Alpha   8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 184 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   AC 97 Controller IP Core   Updated on: 22-May-2007   VLM: 414 This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   ae18   Updated on: 11-Oct-2007   VLM: 280 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 522 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 330 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   Aquarius   Updated on: 04-Jul-2004   VLM: 285 Aquarius is an IP core of pipelined RISC CPU, which is compatible with instruction set of SuperH-2.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   ASPIDA sync/async DLX Core   Updated on: 23-Sep-2005   VLM: 223 The ASPIDA (ASynchronous Processor Ip of the Dlx Architecture) project aims to demonstrate the industrial viability and IP Reuse potential of asynchronous parts by delivering a free, open-source, industrial-quality, asynchronous IP Processor Core...   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Production/Stable   Bluetooth baseband controller   Updated on: 16-Mar-2002   VLM: 409 The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Alpha   CAN Protocol Controller   Updated on: 30-Apr-2008   VLM: 1591 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   DEFLATE   Updated on: 05-Jun-2006   VLM: 80 The deflate is a VHDL implementation of the popular DEFLATE algorithm for data compression. More information on DEFLATE and its implementation are available at the zlib home page http://www.zlib.net/zlib_docs.html   Language :: VHDL License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Alpha   DragonBall/68K Wishbone interface   Updated on: 14-Feb-2004   VLM: 182 WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Ethernet 10GE MAC   Updated on: 07-Jun-2008   VLM: 357 The 10GE MAC implements the MAC layer for 10Gbps operation as defined in 802.3ae. The MAC is designed to be compact while providing the necessary functionally to be compliant.   Category :: Communication controller Language :: SystemC Language :: Verilog License :: LGPL Standard :: Wishbone compliant core Development status :: Beta   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   VLM: 3463 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   FireWire (IEEE 1394)   Updated on: 17-Feb-2003   VLM: 276 FireWire, an Apple trademarked name for IEEE 1394 protocol, is a high performance serial bus protocol to provide easy-to-use, low-cost, high-speed communications   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Planning   General-Purpose I/O (GPIO) Core   Updated on: 16-Jul-2004   VLM: 346 The GPIO IP core is user-programmable general-purpose I/O controller.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   Graphical LCD interfaces   Updated on: 04-Jan-2004   VLM: 441 This project attempts to write WISHBONE compatible VHDL cores that interface to a wide variety of the most popular LCD controller chips.   Category :: Video controller Standard :: Wishbone compliant core Development status :: Beta   HDLC controller   Updated on: 14-Nov-2001   VLM: 428 8 bit parallel backend interface, uses external RX and TX clocks.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   I2C controller core   Updated on: 09-Aug-2008   VLM: 3198 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C master/slave Core   Updated on: 27-Jun-2008   VLM: 807 The design is capable of working as both I2C compatible master and slave.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   I2S Interface   Updated on: 02-Feb-2008   VLM: 731 The I2S bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between a cpu/dsp and a DAC/ADC. This core implements I2S transmitter and receiver.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Image warping/Texture mapping core   Updated on: 02-Aug-2008   VLM: 366 This core maps a texture to an object defined by a grid of control points.   Category :: Video controller Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   Internal Logic State Analyzer   Updated on: 11-Dec-2002   VLM: 191 The internal Logic state Analyser (LA) is a simplified version of a standard logic state analyzer, however it is build-in the prototyped circuit and therefore allows for probing internal signals. The LA at first writes probed signals into its int...   Category :: Prototype board Standard :: Wishbone compliant core Development status :: Beta   IrDA   Updated on: 26-Aug-2002   VLM: 241 WISHBONE-compatible IrDA communication controller.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 25-Aug-2008   VLM: 1267 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Keypad Scanner   Updated on: 16-Jun-2003   VLM: 198 Parameterized module that scans an (X,Y) keypad matrix and reports which key is pressed. Variable scan rate, provides registered outputs.   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 27-Aug-2008   VLM: 629 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Memory Controller IP Core   Updated on: 22-May-2007   VLM: 502 This is an advanced Memory Controller intended for embedded applications.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   Memory sizer   Updated on: 21-Dec-2001   VLM: 201 Automatically sizes memory accesses to fit different types of memory, dynamically. You may read/write DWORDS and WORDS using BYTE wide RAM, etc. Handles little endian and big endian, misaligned accesses etc. Resizable parameterized module. Wri...   Category :: Memory core Standard :: Wishbone compliant core Development status :: Production/Stable   nnARM core   Updated on: 15-Oct-2001   VLM: 758 ARM-7 clone   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Mature   OCIDEC (OpenCores IDE Controller)   Updated on: 04-May-2007   VLM: 582 ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface. The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and...   Category :: System controller Standard :: Wishbone compliant core Development status :: Production/Stable   oks8   Updated on: 24-Jan-2006   VLM: 163 oks8 is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.).   Category :: Microprocessor Language :: Verilog License :: GPL Standard :: Wishbone compliant core Development status :: Alpha   OpenCores54x DSP   Updated on: 20-Jan-2004   VLM: 444 The OC54x DSP is a cleanroom implementation of a popular family of DSPs.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Beta   OpenRISC 1000   Updated on: 20-Aug-2008   VLM: 12042 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   PCI bridge   Updated on: 04-Jul-2006   VLM: 1272 PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   PCI Target   Updated on: 23-Jul-2008   VLM: 708 Simple PCI Target. PCI 32 bits. Whisbone compatible. Tested on Hardware (ALTERA/XILINX). Fits on small FPGA: About 200 LC's (ALTERA CYCLONE II).   Category :: System controller Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   pci_mini   Updated on: 26-Apr-2008   VLM: 499 This is a very small and simple PCI to wishbone bridge. Target only, low bandwidth but easy to use.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   PIF2WB   Updated on: 07-Aug-2007   VLM: 100 PIF2Wishbone bridge   Category :: SoC Language :: VHDL Phaze :: Design done Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta   PLBv46 to Wishbone Bridge   Updated on: 31-Jul-2008   VLM: 345 A simple non-bursting bridge from IBM PLBv46 Bus to Wishbone.   Category :: SoC Language :: VHDL Standard :: Wishbone compliant core Development status :: Beta   PS2 Core   Updated on: 30-Oct-2003   VLM: 256 This is a generic PS/2 UART for adding mice and keyboard to your projects.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Beta   PWM/Timer/Counter (PTC) Core   Updated on: 17-Nov-2006   VLM: 364 PWM/Timer/Counter (PTC) IP core is a user-programmable PWM, Timer and Counter controller. Its use is to implement functions like Pulse Width Modulation (PWM), timer and counter facilities.   Category :: Other Standard :: Wishbone compliant core Development status :: Production/Stable   Raggedstone PCI Spartan-3 board   Updated on: 08-Feb-2007   VLM: 342 This page contains a port of the open pci core ported to Enterpoint's Raggedstone board. The project has been tested under the Linux and Windows versions of the Xilinx ISE. The project tarball includes a Makefile that will generate a working prom...   Category :: Prototype board Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta   ROSETTA Configurable Dot Matrix Display Controller   Updated on: 12-Jun-2006   VLM: 212 The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...   Category :: Video controller Language :: Other Language :: Verilog Language :: VHDL License :: GPL Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Planning   RS232 system controller   Updated on: 24-Feb-2005   VLM: 373 RS232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user write and read registers, and send out reset pulses, via an rs232 serial connection to a "dumb ter...   Category :: System controller Standard :: Wishbone compliant core Development status :: Production/Stable   S1 Core   Updated on: 01-Aug-2008   VLM: 596 The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other...   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   SD/MMC Controller   Updated on: 25-Aug-2008   VLM: 1091 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Serial Uart   Updated on: 21-Jan-2003   VLM: 548 An other version of a tiny Uart. designed to fit in a small FPGA.