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Phaze :: Specification done We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AES core modules   Updated on: 15-May-2007   VLM: 411 AES modules in VHDL. This is base implementation of algorithm described in http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf   Category :: Crypto core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 357 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   External parallel port to internal wishbone master interface   Updated on: 26-Jun-2008   VLM: 138 This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions ar...   Category :: System controller Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   ham_7_4_enc   Updated on: 22-Jun-2004   VLM: 127 Hamming (7,4) encoder: This core encodes every 4-bit information into 7-bit codewords in such a way that any single-bit error can be corrected by the decoder.   Category :: ECC core Language :: Verilog Phaze :: Specification done Development status :: Planning   M1 Core   Updated on: 22-Aug-2008   VLM: 249 The M1 Core is a 32-bit RISC CPU compatible with GCC. It is so simple that it can be used for didactical purposes.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta   PIF2WB   Updated on: 07-Aug-2007   VLM: 95 PIF2Wishbone bridge   Category :: SoC Language :: VHDL Phaze :: Design done Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta   ROSETTA Configurable Dot Matrix Display Controller   Updated on: 12-Jun-2006   VLM: 185 The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...   Category :: Video controller Language :: Other Language :: Verilog Language :: VHDL License :: GPL Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Planning   Sharp LQ057Q3DC02 LCD Controller   Updated on: 04-Jan-2008   VLM: 327 Driver for Sharp LQ057Q3DC02 320x240 QVGA LCD. Driver accurate to datasheet specifications. Will also work for LQ057Q3DC12 (Pb-free version).   Category :: Video controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Development status :: Production/Stable   Simple-CPU SC91-A   Updated on: 07-Oct-2005   VLM: 128 Simple CPU is an open source 32 bits RISC processor based on a load / store architecture written in VHDL. As target, developpement suite will support GCC. Simulator and assembly compilers will be available in Java. Simple CPU is actually impleme...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   Single Clock Unsigned Division Algorithm   Updated on: 23-Apr-2004   VLM: 436 Preface Now two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during o...   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   SPI Flash controller   Updated on: 22-Jun-2007   VLM: 454 This VHDL module implements a state controller for a serial (SPI) Flash ROM.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Development status :: Beta   T8000 CPU   Updated on: 03-Jan-2006   VLM: 200 Configurable CPU that supports Z8000 (Z8001/Z8002) instruction sets.   Category :: Microprocessor Language :: Verilog Phaze :: Specification done Development status :: Alpha   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 23-Sep-2008   VLM: 2779 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable