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Phaze :: Design done We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1-bit Microprocessor   Updated on: 17-Oct-2006   VLM: 540 This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, t...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Development status :: Alpha   10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Sep-2008   VLM: 1795 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 205 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   8080 Compatible CPU   Updated on: 21-Nov-2006   VLM: 583 CPU8080 is a basic 8080 emulation in Verilog. It was completed as a project to learn Verilog, but it can be useful as a very small onchip controller CPU with very modest silicon area requirements. In addition, the 8080 has a long list of softw...   Category :: Microprocessor Language :: Verilog Phaze :: Design done Development status :: Production/Stable   8b10b Encoder/Decoder   Updated on: 05-Oct-2006   VLM: 471 This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limit...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 22-Jul-2008   VLM: 984 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   a VHDL 8254 Timer   Updated on: 24-Aug-2008   VLM: 301 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   A VHDL CAN Protocol Controller   Updated on: 03-Nov-2007   VLM: 470 A VHDL translation of the Verilog CAN Protocol Controller   Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Adaptive LMS equalizer   Updated on: 25-Apr-2006   VLM: 262 This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller Category :: DSP core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Beta   ae18   Updated on: 11-Oct-2007   VLM: 209 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 470 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AES core modules   Updated on: 15-May-2007   VLM: 459 AES modules in VHDL. This is base implementation of algorithm described in http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf   Category :: Crypto core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   AES128   Updated on: 28-Dec-2004   VLM: 460 Advanced Encryption Standard Cryptographic Core   Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   ahb system generator   Updated on: 02-Nov-2007   VLM: 277 It's a PERL/TK script to define and configure an AHB system. A configuration and matrix file is generated comprising arbiters, decoders and master and slave muxes. A complete system file is also generated with AHB simple masters and slaves inst...   Category :: SoC Language :: VHDL Phaze :: Design done Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 400 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   AVRtinyX61core   Updated on: 10-Nov-2008   VLM: 602 Simple ATtiny261/461/861 core in VHDL.   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   boundaries   Updated on: 07-Jul-2004   VLM: 130 A collection of useful multi-clock and clock-boundary designs.   Category :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable   ClaiRISC - runs 12bit opcode PIC family.   Updated on: 05-Aug-2008   VLM: 215 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   configurable cordic core in verilog   Updated on: 25-Sep-2008   VLM: 277 A 100 percent behavioral verilog first quadrant cordic core. The core is highly configurable through defines and can implement a combinatorial, iterative, or pipelined solution of both vector and rotate cordic algorithms. Complete with function...   Category :: Arithmetic core Language :: Verilog Phaze :: Design done Phaze :: FPGA proven   CORDIC core   Updated on: 14-Feb-2004   VLM: 1186 The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Cowgirl   Updated on: 31-May-2007   VLM: 337 This is a processor core based on an instruction set I came up with. It's mostly a copy of a MIPS-type RISC architecture. Right now it's in the fairly early stages, but it is working for ~80% of the instructions.   Category :: Microprocessor Language :: VHDL Phaze :: Design done Development status :: Beta   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 230 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   DEFLATE   Updated on: 05-Jun-2006   VLM: 77 The deflate is a VHDL implementation of the popular DEFLATE algorithm for data compression. More information on DEFLATE and its implementation are available at the zlib home page http://www.zlib.net/zlib_docs.html   Language :: VHDL License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Alpha   DragonBall/68K Wishbone interface   Updated on: 14-Feb-2004   VLM: 151 WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   EBU/spdif to I2S project   Updated on: 29-Nov-2004   VLM: 144 this program in vhdl decodes an EBU/SPDIF input and transforms it to I2s ,   Category :: Communication controller Language :: VHDL Phaze :: Design done   EUS FS - Alice II - Embeddable Single Board Computer   Updated on: 30-Apr-2008   VLM: 238 EUS FS is an "open" system board designed for industrial control and data acquisition applications. It is equipped with a 32-bit CPU working @ 200MHz (Etrax FS), Xilinx's gate array (Spartan 3E) and support electronics.   Category :: Prototype board Phaze :: Design done Development status :: Production/Stable   extension_pack   Updated on: 14-Sep-2006   VLM: 115 a set of low level functions and procedures to expand upon your VHDL   Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Fast Hadamhard Transforms   Updated on: 20-Apr-2007   VLM: 152 The RTL code calculates the Fast Hadamhard transform(FHT) for a 8-bit input data. This has been coded as per the standard algorithm for FHT. It contains matrix elements addition and subtraction in a definite manner. The RTL code given here is syn...   Category :: DSP core Language :: Verilog Phaze :: Design done Development status :: Beta   Functional simulation models for commercially available RAMs   Updated on: 18-Nov-2008   VLM: 148 The simu_mem project provides functional simulation models of commercially available RAMs. The following types are presently supported: - asynchronous static SRAMs - synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT RAM) ...   Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   Gator uProcessor - HC11 Compatible   Updated on: 04-Apr-2008   VLM: 151 Gator Microprocessor Overview * Motorola/Freescale 68xx Architecture * Source-code and machine-code compatible 68HC11 cpu core * Compatible with all HC11 C/C++ compilers including GNU GCC * Up to 100MHz operation in modern FPGAs * 2.5 t...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   gh vhdl library   Updated on: 08-Nov-2008   VLM: 875 A VHDL library of counters, shift registers, and other MSI parts as well as the a dual port RAM, FIFO, the CIC filter, a CORDIC, FIR Filter and TVFD filter   Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Hardware looping unit   Updated on: 19-Oct-2006   VLM: 148 Tha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by efficiently handling loop increments and branches in nested loop structures. It is based on recently published work (deta...   Category :: Other Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline   Updated on: 23-Aug-2008   VLM: 530 HSSDRC is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. The main features of HSSDRC IP core are: 1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to...   Category :: Memory core Language :: Other Phaze :: Design done Development status :: Alpha Development status :: Production/Stable   HPC-16   Updated on: 08-Nov-2006   VLM: 151 Simple 16-bit microprocessor, 15-general purpose registers. custom instruction set, load-store RISC but current implementation non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. design w...   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   HyperTransport Tunnel   Updated on: 23-May-2006   VLM: 178 A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components.   Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Beta   I/Q Constellation diagram on VGA   Updated on: 02-Mar-2008   VLM: 180 Do you have I/Q digital waveforms in your system ? Do you want to have a quick look at them as a constellation but don't have access to a big lump of equipment ? This block takes in a stream of I/Q pairs, and outputs them in a VGA timing fo...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   I2C controller core   Updated on: 03-Nov-2008   VLM: 3289 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C Master Slave Core   Updated on: 29-Oct-2008   VLM: 727 An I2C core, supports multimaster, and can act as a slave. the part of the Master is tested in hardware, the slave is yet to be tested   Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Beta   I2S Interface   Updated on: 19-Sep-2008   VLM: 772 The I2S bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between a cpu/dsp and a DAC/ADC. This core implements I2S transmitter and receiver.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Image warping/Texture mapping core   Updated on: 02-Aug-2008   VLM: 217 This core maps a texture to an object defined by a grid of control points.   Category :: Video controller Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   MAXII-Evalboard   Updated on: 26-Jun-2005   VLM: 276 Evalboard with Altera MAX II CPLD Ideal for learning VHDL Features: - Altera EPM570T100 CPLD - 2-digit LED-matrix display - 4 user-switches + reset - Data-connection to PC via USB-UART FTDI FT232BM-chip - Integrated JTAG-programming ca...   Category :: Prototype board Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Mini AES   Updated on: 28-Dec-2005   VLM: 238 Advanced Encryption Standard (AES) implementation with small area/resources utilization.   Category :: Crypto core Language :: VHDL Phaze :: Design done Development status :: Alpha   NCO / Periodic Waveform Generator   Updated on: 06-Nov-2008   VLM: 999 Numerically Controlled Oscillator (NCO) with various output waveform formats : sin/cos/square/sawtooth. Features a 12-bit data width and 32-bit tuning word. Small and fast permitting 500MHz operation on Xilinx Virtex 5/Altera Stratix III FPGAs....   Category :: DSP core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   OMRP Prototype board v2   Updated on: 29-Jul-2008   VLM: 221 A new open-hardware FPGA-based network router that can be used for mesh wifi networks, as an alternative of ISPs home-gateway, and as a development platform for SoC projects.   Category :: Prototype board Phaze :: Design done Development status :: Production/Stable   OPB-compatible OneWire Master   Updated on: 09-Oct-2007   VLM: 141 This is a OneWire Master core that is fully compatible with the Xilinx OPB specification.   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   OpenRisc 1200 Graphic Configuration Tool   Updated on: 16-Sep-2005   VLM: 177 A Tcl/TK script to graphically configure OpenRisc 1200 microprocessor. Similar to LEON one.   Category :: Other Language :: Other License :: GPL Phaze :: Design done Development status :: Production/Stable   PAL/NTSC encoder   Updated on: 10-Mar-2007   VLM: 650 PAL and NTSC encoders with internal carrier (DDS) and color burst generation. The core with 8 basic colours will fit into a small CPLD and needs rgb-signals, hsync,vsync and a 16/32 Mhz clock. Video output uses 5 resistors on a 75 Ohm load.   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   PCI Board   Updated on: 20-Dec-2005   VLM: 410 A versatile small pci board project based on Spartan-II.   Category :: Prototype board License :: GPL Phaze :: Design done Development status :: Mature   PCI Express x1 16bit VERA testbench   Updated on: 15-Jan-200