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Language :: VHDL We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) (M)JPEG Decoder   Updated on: 30-Oct-2008   VLM: 934 A hardware based system to decode JPEG baseline compressed image data. The different stages of the decoding process are implemented in a pipelined design described in VHDL. Running on a Virtex-II Pro FPGA at 100 MHz operation frequency. The pi...   Category :: Video controller Language :: VHDL License :: GPL Development status :: Beta   1-bit Microprocessor   Updated on: 17-Oct-2006   VLM: 541 This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, t...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Development status :: Alpha   3DES (Triple DES) / DES (VHDL)   Updated on: 01-Dec-2006   VLM: 333 A VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST.   Category :: Crypto core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   5x4Gbps CRC generator designed with standard cells   Updated on: 05-May-2004   VLM: 290 The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells ...   Category :: Arithmetic core Language :: VHDL License :: GPL Development status :: Production/Stable   68hc05   Updated on: 13-May-2007   VLM: 176 Rebuild of Motorola 68HC05 microcontroller only from a datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   68hc08   Updated on: 07-May-2007   VLM: 293 Rebuild of Motorola 68HC08 microcontroller only from datasheet   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   8-bit microcontroller with extended peripheral set   Updated on: 10-Aug-2008   VLM: 310 The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral set. The model should be highly configurable, making it possible to exclude unused peripheral units....   Category :: Microprocessor Language :: VHDL License :: LGPL Development status :: Alpha   8b10b Encoder/Decoder   Updated on: 05-Oct-2006   VLM: 471 This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limit...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 22-Jul-2008   VLM: 978 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   a VHDL 8254 Timer   Updated on: 24-Aug-2008   VLM: 304 a VHDL timer, based upon the Intel 8254   Category :: Other Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   A VHDL CAN Protocol Controller   Updated on: 03-Nov-2007   VLM: 470 A VHDL translation of the Verilog CAN Protocol Controller   Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Adaptive LMS equalizer   Updated on: 25-Apr-2006   VLM: 270 This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller Category :: DSP core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Beta   adat receiver   Updated on: 14-Oct-2008   VLM: 175 This is a feed forward receiver for an 8 channel ADAT lightpipe optical audio datastream. It outputs the audio data on a data bus, user databits on seperate pins, each updated every ADAT frame. It also outputs the recovered wordclock on a pin. ...   Category :: Communication controller Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   AES core modules   Updated on: 15-May-2007   VLM: 460 AES modules in VHDL. This is base implementation of algorithm described in http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf   Category :: Crypto core Language :: VHDL Phaze :: Design done Phaze :: Specification done Development status :: Production/Stable   AES128   Updated on: 28-Dec-2004   VLM: 463 Advanced Encryption Standard Cryptographic Core   Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   ahb system generator   Updated on: 02-Nov-2007   VLM: 283 It's a PERL/TK script to define and configure an AHB system. A configuration and matrix file is generated comprising arbiters, decoders and master and slave muxes. A complete system file is also generated with AHB simple masters and slaves inst...   Category :: SoC Language :: VHDL Phaze :: Design done Development status :: Production/Stable   AMI / HDB1 Line Codes   Updated on: 25-Nov-2007   VLM: 95 VHDL implementation of the AMI --- Alternate Mark Inverse --- and HDB1 --- High Density Bipolar of Order 1 line codes. For HDBn of higher order look at: http://www.opencores.org/projects/hdbn   Category :: Communication controller Language :: VHDL Development status :: Production/Stable   Arm core   Updated on: 26-Apr-2004   VLM: 1144 A free synthesizable arm v4 vhdl model. The framework is made to be extendable for other architectures in the future.   Category :: Microprocessor Category :: SoC Language :: VHDL Development status :: Beta   AVRtinyX61core   Updated on: 10-Nov-2008   VLM: 605 Simple ATtiny261/461/861 core in VHDL.   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   Basic DES Crypto Core   Updated on: 15-Oct-2005   VLM: 236 Fast, small ECB mode DES encryption and decryption. Can be daisychained to implement TripleDES. Additional logic required for CFB, CBC, and other modes.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   Basic RSA Encryption Engine   Updated on: 15-Oct-2005   VLM: 289 A no-frills implementation of the RSA Public Key Encryption algorithm. The design is intended as an exercise in hardware design, and meets only two requirements: 1) It must work. 2) It must fit within a commercially available FPGA.   Category :: Crypto core Language :: VHDL Development status :: Production/Stable   baud generator   Updated on: 20-Dec-2007   VLM: 200 block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse. Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Param...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   BigCounter   Updated on: 02-Jan-2008   VLM: 149 Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic.   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   Camellia cores   Updated on: 23-Jun-2008   VLM: 96 VHDL implementations of Camellia cipher. All block size (128, 192, 256) are supported.   Category :: Crypto core Language :: VHDL License :: GPL Development status :: Beta   Cereon   Updated on: 03-Nov-2007   VLM: 30 A new generation 64-bit RISC microprocessor family targeting a wide niche of applications - from embedded installations to worksations to high-load servers.   Language :: VHDL   Color Converter   Updated on: 26-Feb-2007   VLM: 371 Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...   Category :: Video controller Dependencies :: Other cores Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Configurable Hamming Generator   Updated on: 21-Aug-2007   VLM: 200 This program automatically generates Hamming encoder and decoder for a given word width. It also generates a testbench to evaluate the generate modules.   Category :: ECC core Language :: VHDL License :: GPL Development status :: Production/Stable   CORDIC core   Updated on: 14-Feb-2004   VLM: 1196 The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.   Category :: Arithmetic core Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Cowgirl   Updated on: 31-May-2007   VLM: 338 This is a processor core based on an instruction set I came up with. It's mostly a copy of a MIPS-type RISC architecture. Right now it's in the fairly early stages, but it is working for ~80% of the instructions.   Category :: Microprocessor Language :: VHDL Phaze :: Design done Development status :: Beta   Cpu Generator   Updated on: 03-Mar-2004   VLM: 521 CpuGen (TM) generates customizable RISC cpu cores. It allows direct customization of address/data/instruction bus size, interrupt handling, indirect addressing, data/instruction latency timings and custom instructions definition. It is targeted...   Category :: Microprocessor Language :: VHDL Development status :: Production/Stable   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 229 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   cpu65c02_tc - 65C02 Processor Soft Core with accurate timing   Updated on: 13-Aug-2008   VLM: 131 The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer. It comes also with ...   Category :: Microprocessor Language :: VHDL License :: GPL Development status :: Beta   Crypto-PAn   Updated on: 17-Feb-2007   VLM: 101 A hardware implementation of Prefix-Preserving IP Address Anonymization. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the underlying pseudorandom function, supports online key changes, and is capable of line rat...   Category :: Crypto core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Data Flow Processor   Updated on: 02-Nov-2008   VLM: 385 The data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire design. It is composed of 7 components with a specific data flow architecture. Please see http://www....   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   DEFLATE   Updated on: 05-Jun-2006   VLM: 77 The deflate is a VHDL implementation of the popular DEFLATE algorithm for data compression. More information on DEFLATE and its implementation are available at the zlib home page http://www.zlib.net/zlib_docs.html   Language :: VHDL License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Alpha   Diogenes: Student RISC System   Updated on: 04-Feb-2008   VLM: 163 This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture and features * Assembler * Simulator * Simple I/O (Leds, Buttons, UART, LCD) * VGA Controller Please note that it was developed ...   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Beta   Discrete Cosine Transform core   Updated on: 30-Oct-2008   VLM: 535 Parallel implementation of 2D DCT in VHDL. Currently works on 8 bit input data using 12 bit DCT coefficients. Multiplier-less design, distributed arithmetic used instead.   Category :: Arithmetic core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   DWT coprocessor on still image   Updated on: 24-Jan-2005   VLM: 166 This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The project is simulated on ModelSim 5.7g and going to implement on Spartan-3 Starter Kit.   Category :: Other Language :: VHDL Development status :: Beta   E1 Framer/Deframer   Updated on: 04-May-2007   VLM: 240 CCITT G.704,G.706 E1 framer for 30 64kbps voice/data channel framing at 2.048 MHz bit rate.   Category :: Communication controller Language :: VHDL Development status :: Planning   EBU/spdif to I2S project   Updated on: 29-Nov-2004   VLM: 145 this program in vhdl decodes an EBU/SPDIF input and transforms it to I2s ,   Category :: Communication controller Language :: VHDL Phaze :: Design done   extension_pack   Updated on: 14-Sep-2006   VLM: 116 a set of low level functions and procedures to expand upon your VHDL   Category :: Library Language :: VHDL Phaze :: Design done Development status :: Production/Stable   External parallel port to internal wishbone master interface   Updated on: 26-Jun-2008   VLM: 116 This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions ar...   Category :: System controller Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   FirGen/MultGen   Updated on: 28-Mar-2008   VLM: 406 VHDL core generator for FIR filters and Multiplier arrays with common input using "Nonrecursive Signed Common Subexpression Algorithm" for optimization program writen on C++ -------------------------- firgen [OPTION..] Aviable options ar...   Category :: DSP core Language :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   First File Reader FAT16   Updated on: 10-May-2004   VLM: 272 This Core reads from a Compact Flash attached to its IDE interface the first valid file saved into the root directory of a FAT16 volume. The data are offered to a Wishbone bus through a slave WB interface.   Category :: Other Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   FPU   Updated on: 29-Jun-2008   VLM: 1144 The floating point unit (FPU) implemented during this project, is a 32-bit processing unit, which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.   Category :: Arithmetic core Category :: Coprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   Full Stepper Control   Updated on: 29-Jun-2008   VLM: 290 Using a FSM I generate controller for motor step by step. It possible to choose direction of spin, modality and enable or not of the controller.   Category :: System controller Language :: VHDL Development status :: Production/Stable   Functional simulation models for commercially available RAMs   Updated on: 18-Nov-2008   VLM: 146 The simu_mem project provides functional simulation models of commercially available RAMs. The following types are presently supported: - asynchronous static SRAMs - synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT RAM) ...   Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   Fuzzy Logic Hardware Accelerator   Updated on: 07-Apr-2004   VLM: 167 This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have ...   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   Gamepads   Updated on: 15-Sep-2005   VLM: 220 A collection of cores that interface to various gamepads.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   Gator uProcessor - HC11 Compatible   Updated on: 04-Apr-2008   VLM: 152 Gator Microprocessor Overview * Motorola/Freescale 68xx Architecture * Source-code and machine-code compatible 68HC11 cpu core * Compatible with all HC11 C/C++ compilers including GNU GCC * Up to 100MHz operation in modern FPGAs * 2.5 t...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   GECKO3 SoC co-design environment   Updated on: 04-Nov-2008