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Language :: Verilog We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AES (Rijndael) IP Core   Updated on: 22-May-2007   VLM: 680 AES (Rijndael) IP Core. Complete with cipher and inverse cipher and key expansion block. Everything written in Verilog - high performace, small area.   Category :: Crypto core Language :: Verilog Development status :: Production/Stable   1 GigEthernet MAC core   Updated on: 20-Jan-2006   VLM: 339 Main Features IEEE 802.3-2002 compliant Supports only full duplex operations Supports full duplex flow control FCS generation for transmit, check for receiving packets. GMII interface to PHY layer and Simple application interface. Simple Ho...   Category :: Communication controller Language :: Verilog Development status :: Planning   10G Ethernet MAC   Updated on: 10-Apr-2008   VLM: 469 The 10G ethernet mac core. It is compliant with ieee 802.3ae. Transmit engine and Receive engine have been finished.   Category :: Communication controller Language :: Verilog Development status :: Alpha   10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Aug-2008   VLM: 1522 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   128/192 AES   Updated on: 19-Sep-2005   VLM: 433 A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications. The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block. The 192 bit implementation takes about 280 cycles to encrypt/decrypt a b...   Category :: Crypto core Language :: Other Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   802.3an LDPC Decoder   Updated on: 20-Feb-2007   VLM: 365 LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm.   Category :: ECC core Language :: Verilog Development status :: Production/Stable   802.3an LDPC Encoder   Updated on: 20-Feb-2007   VLM: 300 A low-density parity-check encoder for the recently ratified 10GBASE-T standard (802.3an).   Category :: ECC core Language :: Verilog Development status :: Production/Stable   8051 Slave to Wishbone Master Interface   Updated on: 25-Jul-2008   VLM: 185 Interface an 8051-compatible microcontroller controller to the Wishbone bus.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   8080 Compatible CPU   Updated on: 21-Nov-2006   VLM: 524 CPU8080 is a basic 8080 emulation in Verilog. It was completed as a project to learn Verilog, but it can be useful as a very small onchip controller CPU with very modest silicon area requirements. In addition, the 8080 has a long list of softw...   Category :: Microprocessor Language :: Verilog Phaze :: Design done Development status :: Production/Stable   AC 97 Controller IP Core   Updated on: 22-May-2007   VLM: 412 This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   ae18   Updated on: 11-Oct-2007   VLM: 279 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 30-Jul-2008   VLM: 523 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 322 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   An Alternative Oscilloscope   Updated on: 29-Oct-2005   VLM: 353 AlternaScope provides a cheap alternative to those pricey oscilloscopes on the market. Using a VGA display and a simple mouse interface, a user can use this scope to look at and measure signals up to about 80Mhz. This kind of scope would be ide...   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Beta   boundaries   Updated on: 07-Jul-2004   VLM: 136 A collection of useful multi-clock and clock-boundary designs.   Category :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable   ClaiRISC - runs 12bit opcode PIC family.   Updated on: 05-Aug-2008   VLM: 352 This is another RISC core which is compatible with the 12 bit opcode PIC family.   Category :: Microprocessor Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   DES/Triple DES IP Cores   Updated on: 22-May-2007   VLM: 419 Traditional DES and Triple DES IP Cores.   Category :: Crypto core Language :: Verilog Development status :: Production/Stable   DragonBall/68K Wishbone interface   Updated on: 14-Feb-2004   VLM: 182 WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.   Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Educational RISC Processor   Updated on: 25-Sep-2007   VLM: 348 8-bit RISC processor core written in Verilog HDL. It is capable of executing the Load, Move, Jump, Arithematic and Logical instructions. Core customization is quite simple and a lot more functionality can be included like interrupt etc.   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   EMPER E123MUX/DEMUX Core   Updated on: 10-Aug-2005   VLM: 81 FEATURES 1. E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) 2. Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip ...   Language :: Verilog Phaze :: FPGA proven Development status :: Beta   Ethernet 10GE MAC   Updated on: 07-Jun-2008   VLM: 359 The 10GE MAC implements the MAC layer for 10Gbps operation as defined in 802.3ae. The MAC is designed to be compact while providing the necessary functionally to be compliant.   Category :: Communication controller Language :: SystemC Language :: Verilog License :: LGPL Standard :: Wishbone compliant core Development status :: Beta   Fast Hadamhard Transforms   Updated on: 20-Apr-2007   VLM: 167 The RTL code calculates the Fast Hadamhard transform(FHT) for a 8-bit input data. This has been coded as per the standard algorithm for FHT. It contains matrix elements addition and subtraction in a definite manner. The RTL code given here is syn...   Category :: DSP core Language :: Verilog Phaze :: Design done Development status :: Beta   Floating Point Unit   Updated on: 10-Jan-2005   VLM: 570 This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions.   Category :: Coprocessor Language :: Verilog Development status :: Production/Stable   FPGA MMC-Card Config.   Updated on: 09-Jan-2005   VLM: 259 IP Core to configure RAM based FPGA from MMC Card.   Category :: Other Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   Generic FIFOs   Updated on: 11-Feb-2004   VLM: 674 Generic, multiple purpose, parameterizable FIFOs. Single and Dual Clock.   Category :: Memory core Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   gsc   Updated on: 28-Aug-2007   VLM: 198 gnu systemc compiler - a systemc collection of tools, including a systemc to verilog translator.   Category :: Other Language :: SystemC Language :: Verilog License :: GPL Development status :: Beta Development status :: Production/Stable   H.264/AVC Baseline Decoder   Updated on: 06-May-2008   VLM: 1065 This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Production/Stable   ham_7_4_enc   Updated on: 22-Jun-2004   VLM: 131 Hamming (7,4) encoder: This core encodes every 4-bit information into 7-bit codewords in such a way that any single-bit error can be corrected by the decoder.   Category :: ECC core Language :: Verilog Phaze :: Specification done Development status :: Planning   I2C controller core   Updated on: 09-Aug-2008   VLM: 3210 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C master/slave Core   Updated on: 27-Jun-2008   VLM: 808 The design is capable of working as both I2C compatible master and slave.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   Image warping/Texture mapping core   Updated on: 02-Aug-2008   VLM: 360 This core maps a texture to an object defined by a grid of control points.   Category :: Video controller Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   In System Programming via JTAG port   Updated on: 19-Jul-2008   VLM: 187 With a PC program, a JTAG cable, and a JTAG ciruit (realized in a cpld), you can program a memory chip, such as Flash or EEprom.   Category :: Other Language :: Verilog Development status :: Planning   M1 Core   Updated on: 22-Aug-2008   VLM: 546 The M1 Core is a 32-bit RISC CPU compatible with GCC. It is so simple that it can be used for didactical purposes.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta   M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 27-Aug-2008   VLM: 638 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Macroblock Motion Detection   Updated on: 16-Dec-2004   VLM: 40 Motion detection for macroblocks in image frames   Language :: Verilog Development status :: Alpha   MCPU - A minimal CPU for a CPLD   Updated on: 29-Jul-2008   VLM: 889 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   Memory Controller IP Core   Updated on: 22-May-2007   VLM: 500 This is an advanced Memory Controller intended for embedded applications.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   Mini-Risc core   Updated on: 22-May-2007   VLM: 927 This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 from Microchip. Additional information about the instruction set and capabilities can be found at: www.microchip.com   Category :: Microprocessor Language :: Verilog Development status :: Production/Stable   mips789   Updated on: 07-Apr-2008   VLM: 326 This is a ip cpu core with five pipeline stages which supports amost MIPSI instructions.I tested is by using a lot of C program in the CYCLONE device EP1C6Q240 with 50MHZ and it worked so well .By calculation ,it's CPI is about 1.1 when run comm...   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   MOST Network Interface Controller   Updated on: 25-Dec-2005   VLM: 162 Media Oriented Systems Transport is a multimedia fiber-optic network optimized for automotive applications. It is a network developed by the automotive industry for the automotive industry. Its design allows it to provide a low-overhead and low-c...   Category :: Communication controller Dependencies :: Technology Language :: Verilog Development status :: Planning   nCore   Updated on: 28-Oct-2007   VLM: 196 This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc. but it's ready to compile.   Category :: Microprocessor Language :: Verilog License :: GPL Development status :: Alpha   oks8   Updated on: 24-Jan-2006   VLM: 162 oks8 is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.).   Category :: Microprocessor Language :: Verilog License :: GPL Standard :: Wishbone compliant core Development status :: Alpha   OPB-compatible OneWire Master   Updated on: 09-Oct-2007   VLM: 117 This is a OneWire Master core that is fully compatible with the Xilinx OPB specification.   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   OPB-compatible VGA character display, no DAC   Updated on: 17-Oct-2007   VLM: 289 This is an OPB-compatible VGA character display for the Spartan 3E development board, which does not contain DACs. The core is very small, requiring only 3 BRAMs and 533 slices. All access is through write character commands, similar to an ...   Category :: Video controller Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   OpenFIRE   Updated on: 16-Oct-2007   VLM: 403 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by S...   Category :: Microprocessor Category :: SoC Language :: Verilog Phaze :: FPGA proven Development status :: Beta   OpenFire Processor Core   Updated on: 13-Dec-2007   VLM: 238 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze processor. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire processor...   Category :: Microprocessor Language :: Verilog Phaze :: FPGA proven Development status :: Alpha   OpenRISC 1000   Updated on: 20-Aug-2008   VLM: 12028 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   openVeriFLA - FPGA logic analyzer   Updated on: 03-Mar-2008   VLM: 254 No description provided   Category :: Library Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   PCI bridge   Updated on: 04-Jul-2006   VLM: 1270 PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   PCI E