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Updated on: 07-Jul-2008
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VLM: 645
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BSV implementation of H.264 Video decoder.
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Category :: Video controller
Language :: Other
Phaze :: FPGA proven
Development status :: Beta
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Updated on: 26-Feb-2007
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VLM: 340
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Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...
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Category :: Video controller
Dependencies :: Other cores
Language :: VHDL
License :: LGPL
License :: GPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 04-Jan-2004
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VLM: 440
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This project attempts to write WISHBONE compatible VHDL cores that interface to a wide variety of the most popular LCD controller chips.
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Category :: Video controller
Standard :: Wishbone compliant core
Development status :: Beta
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Updated on: 06-May-2008
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VLM: 1065
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This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...
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Category :: Video controller
Language :: Verilog
Phaze :: ASIC proven
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 02-Mar-2008
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VLM: 186
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Do you have I/Q digital waveforms in your system ?
Do you want to have a quick look at them as a constellation but don't have access to a big lump of equipment ?
This block takes in a stream of I/Q pairs, and outputs them in a VGA timing fo...
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Category :: Video controller
Language :: VHDL
License :: LGPL
Phaze :: Design done
Development status :: Beta
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Updated on: 02-Aug-2008
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VLM: 360
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This core maps a texture to an object defined by a grid of control points.
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Category :: Video controller
Language :: Verilog
License :: GPL
Phaze :: Design done
Standard :: Wishbone compliant core
Development status :: Beta
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Updated on: 12-Mar-2008
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VLM: 598
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This is an open source JPEG codec, including both encoder and decoder, for embedded systems. It can be fully synthesized and implemented on FPGA.
Different to a fully hardware implementation, this JPEG codec is designed based on Xilinx Microbl...
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Category :: Video controller
Language :: VHDL
License :: GPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 25-Feb-2008
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VLM: 816
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This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is...
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Category :: Video controller
Language :: VHDL
License :: LGPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 15-Oct-2001
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VLM: 551
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LCD Driver that we want to designed is a CMOS LCD driver capable of driving a multiplexed display of up to 128 segments ( 16 columns by 8 backplanes ).
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Category :: Video controller
Development status :: Beta
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Updated on: 17-Jun-2008
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VLM: 329
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Simple memory mapped, character type dot matrix LCD controller for interfacing the Samsung's KS0073.
The controller supports the 40SEG extension driver providing a 4-line x 20 character display.
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Category :: Video controller
Language :: VHDL
License :: LGPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 09-Apr-2007
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VLM: 308
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The MiniGA is a small graphics adapter for microcontroller which outputs a fully digitally synthesized PAL video signal for TVs, VCRs and video TFTs.
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Category :: Video controller
Language :: VHDL
Development status :: Beta
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Updated on: 09-Apr-2008
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VLM: 395
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This VHDL macro is a simple monochrome text-mode VGA Video Display Adapter (also referred to as video card). This kind of IP core, apart from to let you put text to the screen in your Pico/MicroBlaze SoC designs, may be useful (say) to debug inte...
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Category :: Video controller
Language :: VHDL
License :: LGPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 20-Jun-2008
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VLM: 400
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A MPMC4 NPI video frame buffer interface with configurable VGA controller.
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Category :: Video controller
Language :: VHDL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 17-Oct-2007
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VLM: 289
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This is an OPB-compatible VGA character display for the Spartan 3E development board, which does not contain DACs.
The core is very small, requiring only 3 BRAMs and 533 slices.
All access is through write character commands, similar to an ...
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Category :: Video controller
Language :: Verilog
License :: GPL
Phaze :: FPGA proven
Development status :: Production/Stable
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Updated on: 10-Mar-2007
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VLM: 589
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PAL and NTSC encoders with internal carrier (DDS) and color burst generation. The core with 8 basic colours will fit into a small CPLD and needs rgb-signals, hsync,vsync and a 16/32 Mhz clock. Video output uses 5 resistors on a 75 Ohm load.
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Category :: Video controller
Language :: VHDL
License :: LGPL
Phaze :: Design done
Development status :: Production/Stable
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Updated on: 12-Jun-2006
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VLM: 213
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The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...
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Category :: Video controller
Language :: Other
Language :: Verilog
Language :: VHDL
License :: GPL
Phaze :: Specification done
Standard :: Wishbone compliant core
Development status :: Planning
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Updated on: 04-Jan-2008
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VLM: 362
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Driver for Sharp LQ057Q3DC02 320x240 QVGA LCD. Driver accurate to datasheet specifications. Will also work for LQ057Q3DC12 (Pb-free version).
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Category :: Video controller
Language :: VHDL
License :: GPL
Phaze :: Design done
Phaze :: FPGA proven
Phaze :: Specification done
Development status :: Production/Stable
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Updated on: 01-Aug-2008
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VLM: 396
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This core maps a portion of the main memory to a VGA screen.
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Category :: Video controller
Language :: Verilog
License :: GPL
Phaze :: FPGA proven
Standard :: Wishbone compliant core
Development status :: Production/Stable
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Updated on: 24-Dec-2004
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VLM: 405
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The LCD controller is based on ARM Platform for
Hitachi 7" LCD Panel 'tx18d16vm1caa'
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Category :: Video controller
Dependencies :: Technology
Language :: Verilog
License :: GPL
Phaze :: FPGA proven
Development status :: Planning
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Updated on: 13-May-2004
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VLM: 1542
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The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.
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Category :: Video controller
Language :: Verilog
Phaze :: ASIC proven
Phaze :: Design done
Phaze :: FPGA proven
Standard :: Wishbone compliant core
Development status :: Production/Stable
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Updated on: 27-Aug-2008
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VLM: 1914
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The Video Systems project is a collection of readily available blocks to build different types of compression standards, like H.310, H.320, MPEG-1, MPEG-2 etc.
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Category :: Video controller
Development status :: Production/Stable
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Updated on: 27-Nov-2006
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VLM: 908
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This Video Starter kit is meant for people who want to start with FPGA design.
The kit can be used with free tooling only. There is no need for an extra JTAG device or so. (only needed for on-chip debugging)
Within the project there will be ...
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Category :: Prototype board
Category :: Video controller
Language :: Other
Language :: VHDL
Development status :: Beta
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Updated on: 15-Oct-2001
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VLM: 347
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Wishbone Monitor Controller is a set of freely available VHDL cores. It contains a central building block containing the basic functionality. It can then be sorrounded by various helper functions to add functionality.
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Category :: Video controller
Standard :: Wishbone compliant core
Development status :: Beta
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