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Category :: System controller We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) AC 97 Controller IP Core   Updated on: 22-May-2007   VLM: 382 This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   External parallel port to internal wishbone master interface   Updated on: 26-Jun-2008   VLM: 116 This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions ar...   Category :: System controller Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   Full Stepper Control   Updated on: 29-Jun-2008   VLM: 290 Using a FSM I generate controller for motor step by step. It possible to choose direction of spin, modality and enable or not of the controller.   Category :: System controller Language :: VHDL Development status :: Production/Stable   Memory Controller IP Core   Updated on: 22-May-2007   VLM: 540 This is an advanced Memory Controller intended for embedded applications.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   OCIDEC (OpenCores IDE Controller)   Updated on: 04-May-2007   VLM: 465 ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface. The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and...   Category :: System controller Standard :: Wishbone compliant core Development status :: Production/Stable   PCI bridge   Updated on: 04-Jul-2006   VLM: 1368 PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   PCI Express x1 16bit VERA testbench   Updated on: 15-Jan-2008   VLM: 305 This is a great starter testbench for PCI Express. It performs link management; Initial Flow control; tlp packet generation. It includes lcrc generation; scrambling/descrambling and   Category :: System controller Language :: Other Phaze :: Design done   PCI Target   Updated on: 23-Jul-2008   VLM: 640 Simple PCI Target. PCI 32 bits. Whisbone compatible. Tested on Hardware (ALTERA/XILINX). Fits on small FPGA: About 200 LC's (ALTERA CYCLONE II).   Category :: System controller Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   pci_mini   Updated on: 26-Apr-2008   VLM: 372 This is a very small and simple PCI to wishbone bridge. Target only, low bandwidth but easy to use.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   RS232 system controller   Updated on: 24-Feb-2005   VLM: 490 RS232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user write and read registers, and send out reset pulses, via an rs232 serial connection to a "dumb ter...   Category :: System controller Standard :: Wishbone compliant core Development status :: Production/Stable   scsi_chip   Updated on: 08-Oct-2008   VLM: 166 this is a interface between SCSI and 32 bit procesor, with other features, first proyect   Category :: System controller Language :: Verilog Development status :: Alpha   Synchronous-DRAM Controller   Updated on: 15-Oct-2001   VLM: 277 The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specific...   Category :: System controller Development status :: Alpha   TI DSP and Xilinx FPGA Dev Board   Updated on: 13-Dec-2005   VLM: 608 An FPGA and DSP development board with cPCI interface. Project aims to provide a low cost development platform for DSP and FPGA algorithms implementation. The dev board provides several means for interfacing user-developed hardware. This project ...   Category :: Prototype board Category :: System controller Language :: Other Language :: Verilog Phaze :: Design done Development status :: Production/Stable