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Category :: SoC We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) ahb system generator   Updated on: 02-Nov-2007   VLM: 254 It's a PERL/TK script to define and configure an AHB system. A configuration and matrix file is generated comprising arbiters, decoders and master and slave muxes. A complete system file is also generated with AHB simple masters and slaves inst...   Category :: SoC Language :: VHDL Phaze :: Design done Development status :: Production/Stable   AHB to Wishbone Bridge   Updated on: 07-Sep-2007   VLM: 357 Converts AHB protocol to Wishbone protocol for interfacing two SoC's (AHB Master and Wishbone Slave).   Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature   Arm core   Updated on: 26-Apr-2004   VLM: 1004 A free synthesizable arm v4 vhdl model. The framework is made to be extendable for other architectures in the future.   Category :: Microprocessor Category :: SoC Language :: VHDL Development status :: Beta   Complete SoC based on C-NIT processor   Updated on: 23-Feb-2004   VLM: 133 The goal is to develop a complete SoC based on C-NIT 16 bit CPU. Current implementation includes - C-NIT processor - SDRAM controller. - Cache controller. - LCD and 7 segment drivers. - Keyboard controller. - Glue logic. An assembler f...   Category :: SoC Development status :: Production/Stable   Embedded 32-bit RISC uProcessor with SDRAM Controller   Updated on: 26-Jul-2002   VLM: 204 SOC with Embedded 32-bit mini RISC uProcessor and a SDRAM PC100 CL2 Controller. Five Stage RISC uProcessor 16MB SDRAM Space 2MB Flash Space DMA Bus Arbiter Serial-to-Parallel Converter PIO Interface Timer Watch-Dog Cache   Category :: SoC Development status :: Planning   GECKO3 SoC co-design environment   Updated on: 23-Sep-2008   VLM: 502 The GECKOsystem is a general purpose hardware/software co-design environment for real-time information processing for system-on-chip (SoC) solutions. The GECKO system supports a new design methodology for system-on-chips, which necessitates co-de...   Category :: Prototype board Category :: SoC Dependencies :: Other cores Language :: Other Language :: SystemC Language :: Verilog Language :: VHDL License :: LGPL Development status :: Production/Stable   kiss-board   Updated on: 24-Jul-2008   VLM: 314 BOARD consists of two pieces. One is FPGA board. Another is MOTHER board. The device on the FPGA board is ANY(xilinx or altera ...). Only connected specification of the board is important.   Category :: Prototype board Category :: SoC Development status :: Production/Stable   MP3 decoder   Updated on: 05-Jul-2005   VLM: 562 This project is to implement an MP3 decoder in VHDL without a processor core. Right now, three main modules of MP3 decoding process have been accomplished:Huffman decoder, IMDCT and Filterbank. These components are written in VDHL and the funct...   Category :: SoC Development status :: Alpha   NoCem -- Network on Chip emulator   Updated on: 12-Jul-2007   VLM: 198 A Network on Chip Emulation Tool, NoCem is a body of VHDL code configurable by a toplevel package file that can create a variety of Network on Chips on parameters of datawidth, virtual channel implementations, topology, and in-network buffering l...   Category :: SoC Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   OpenFIRE   Updated on: 16-Oct-2007   VLM: 410 The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by S...   Category :: Microprocessor Category :: SoC Language :: Verilog Phaze :: FPGA proven Development status :: Beta   PIF2WB   Updated on: 07-Aug-2007   VLM: 95 PIF2Wishbone bridge   Category :: SoC Language :: VHDL Phaze :: Design done Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta   PLBv46 to Wishbone Bridge   Updated on: 31-Jul-2008   VLM: 139 A simple non-bursting bridge from IBM PLBv46 Bus to Wishbone.   Category :: SoC Language :: VHDL Standard :: Wishbone compliant core Development status :: Beta   rfid tag and reader   Updated on: 08-Nov-2006   VLM: 148 Verilog version of RFID tag model   Category :: SoC Language :: Verilog License :: GPL Development status :: Beta   SardMIPS   Updated on: 09-Feb-2006   VLM: 221 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting ...   Category :: Microprocessor Category :: SoC Language :: Other License :: GPL Development status :: Alpha   SimpCon - a Simple SoC Interconnect   Updated on: 13-Nov-2007   VLM: 167 SimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for pipelining of read and write connections. SimpCon is public domain and freely available. Transla...   Category :: SoC License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   Soft MultiProcessor on FPGA   Updated on: 12-Mar-2008   VLM: 453 DMA is becoming popular for communication between multiprocessors on SoC or FPGA. This design is a template consisting of four Xilinx microblaze processors and external memory controller connected by a central DMA engine. Compared to fixed bus, F...   Category :: SoC Language :: VHDL License :: GPL Development status :: Beta   system05   Updated on: 07-Apr-2008   VLM: 131 6805 compatible microcomputer.   Category :: Microprocessor Category :: SoC Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   System09   Updated on: 31-Aug-2008   VLM: 348 6809 instruction compatible microprocessor core. SOC version includes UART, Compact Flash Interface, Monitor ROM Simple Video Display, PS/2 keyboard interface and 16 bytes of Dynamic Address Translation Registers   Category :: Microprocessor Category :: SoC Language :: VHDL License :: GPL Development status :: Production/Stable   uAlpha - EV4 (DEC ) RISC easy implementation (uC)   Updated on: 28-Jan-2007   VLM: 172 The main idea of this project is to implement simple RISC processor with Alpha (EV4) instruction set.   Category :: Microprocessor Category :: SoC Language :: Verilog Language :: VHDL Development status :: Planning   WB/OPB & OPB/WB Interface Wrapper   Updated on: 12-Sep-2004   VLM: 178 Interface wrappers between OPB and WISHBONE buses   Category :: SoC Language :: Other Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone BFM   Updated on: 21-Feb-2008   VLM: 261 VHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master. Used in testing a Wishbone peripheral with out having to instantiate and program a 'CPU' function.   Category :: Microprocessor Category :: SoC Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   WISHBONE Builder   Updated on: 09-Jun-2008   VLM: 485 A WISHBONE interconnect matrix generator written in PERL/Tk. Generates HDL from a text description or via GUI input.   Category :: SoC Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Production/Stable   WISHBONE Conbus IP Core   Updated on: 02-Jan-2005   VLM: 191 This is a WISHBONE Interconnect Sharebus IP core.It can interconnect up to 8 Masters and 8 Slaves . The aim of this IP core is to using sharebus which can get higher speed and less logic resource.   Category :: SoC Standard :: Wishbone compliant core Development status :: Production/Stable   WISHBONE Conmax IP Core   Updated on: 10-Feb-2004   VLM: 210 This is a WISHBONE Interconnect Matrix IP core. It can interconnect up to 8 Masters and 16 Slaves   Category :: SoC Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   WISHBONE DMA/Bridge IP Core   Updated on: 22-May-2007   VLM: 341 This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.   Category :: SoC Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   wishbone out port from b3 spec   Updated on: 29-Jan-2008   VLM: 120 Rather cheeky this, but do you like me need a simple wishbone compliant thing to check your wishbone interface against. Well in the wishbone specification Appendix A, we have a bunch of such bits defined in VHDL. So thought I'd put them in...   Category :: SoC Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone System6800/01   Updated on: 10-Mar-2004   VLM: 187 WishBone Based System including: Motorola 6800/01 CPU Core MiniUart similar to Motorola 6850 ACIA Internal ROM Debug Monitor (2048Bytes) Internal 128 Byte RAM External RAM Interface   Category :: SoC Language :: VHDL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone to AHB Bridge   Updated on: 07-Sep-2007   VLM: 270 Converts the Wishbone protocol to AHB protocol   Category :: SoC Dependencies :: Other cores Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   WishboneTK toolkit   Updated on: 04-Jun-2008   VLM: 361 WhisboneTK is a set of IP cores designed to be compatible with the Wishbone bus specification. The members of the tool-kit are general purpose building-blocks whose (hopefuly) make designing Wishbone compatible devices easier..   Category :: SoC Standard :: Wishbone compliant core Development status :: Beta   Z80 System on Chip   Updated on: 16-Jun-2008   VLM: 403 System on chip, based on T80 core. Version 0.6-DE1 is designed for Altera DE1 development board. Version 0.6-S3E is the port for Diligent Spartan 3E. Both projects provide access to leds, switches, buttons, keyboard and vga. DE1 version hav...   Category :: SoC Dependencies :: Other cores Language :: VHDL Development status :: Production/Stable