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Category :: ECC core We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 802.3an LDPC Decoder   Updated on: 20-Feb-2007   VLM: 365 LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm.   Category :: ECC core Language :: Verilog Development status :: Production/Stable   802.3an LDPC Encoder   Updated on: 20-Feb-2007   VLM: 300 A low-density parity-check encoder for the recently ratified 10GBASE-T standard (802.3an).   Category :: ECC core Language :: Verilog Development status :: Production/Stable   CF LDPC Decoder   Updated on: 08-May-2008   VLM: 228 Confluence generated low-density parity-check (LDPC) decoder.   Category :: ECC core Development status :: Production/Stable   Configurable Hamming Generator   Updated on: 21-Aug-2007   VLM: 221 This program automatically generates Hamming encoder and decoder for a given word width. It also generates a testbench to evaluate the generate modules.   Category :: ECC core Language :: VHDL License :: GPL Development status :: Production/Stable   Constellation Encoder   Updated on: 07-Jan-2002   VLM: 125 The requirment of a constellation encoder is described in ITU-T G. 992.1. A cyclic redundancy check (CRC), scrambling, and forward error correction (FEC) coding shall be applied to the contents of data, and the data from the interleaved buffer ...   Category :: ECC core Development status :: Planning   ham_7_4_enc   Updated on: 22-Jun-2004   VLM: 131 Hamming (7,4) encoder: This core encodes every 4-bit information into 7-bit codewords in such a way that any single-bit error can be corrected by the decoder.   Category :: ECC core Language :: Verilog Phaze :: Specification done Development status :: Planning   PCI Express 16 bit CRC verilog file   Updated on: 17-Dec-2007   VLM: 263 This file will generate the LCRC for PCI Express TLP's packets. It takes in 16 bits parallel at a time. All data of the TLP packet including the sequence number and TD bit should be passed through the CRC code.   Category :: ECC core Language :: Verilog Development status :: Production/Stable   Product Code Iterative Decoder   Updated on: 16-Jan-2006   VLM: 97 An iterative decoder for Product Code, this decoder works for two dimensional Product Code.   Category :: ECC core Language :: VHDL Phaze :: Design done Development status :: Beta   Reed Solomon Encoder   Updated on: 14-May-2008   VLM: 425 Reed Solomon Encoder synthesizable IP core compatible with G709, DVB1, DVB2 standards. Implements (n, k) code where n-k = 16 ( 8 byte error correction capable code). The verilog is written in such a way as to be easily parameterized for differ...   Category :: ECC core Language :: Verilog Phaze :: Design done Development status :: Production/Stable   Reed-Solomon Decoder (31, 19, 6)   Updated on: 29-Feb-2008   VLM: 314 Specifications: 1. Hard-decision decoding scheme 2. Codeword length (n) : 31 symbols. 3. Message length (k) : 19 symbols. 4. Error correction capability (t) : 6 symbols 5. One symbol represents 5 bit. 6. Use GF(2^5) with primitive polynomia...   Category :: ECC core Language :: Verilog Phaze :: Design done Development status :: Production/Stable   RS_5_3_GF256   Updated on: 20-Jun-2005   VLM: 114 Reed Solomon (5,3) Coder-Decoder in GF(256): This codec takes a byte (8-bits) as a symbol and encodes the 3-byte information into a 5-byte code word. The decoder is capable of correcting a single-byte error (even if all 8-bits are erronous) amon...   Category :: ECC core Language :: Verilog Phaze :: Design done   Turbo Decoder   Updated on: 14-Jun-2005   VLM: 262 Double binary, DVB-RCS code, Soft Output Viterbi Algorithm, MyHDL model and testbench, synthesizable VHDL model   Category :: ECC core Language :: VHDL License :: LGPL Development status :: Beta   Ultimate CRC   Updated on: 22-Oct-2007   VLM: 344 Ultimate CRC is a CRC generator/checker. Using generics it can be configured for any polynomial, data width and initialization value, using either serial or parallel implementation, synchronous or asynchronous reset.   Category :: ECC core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable