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Category :: Communication controller We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1 GigEthernet MAC core   Updated on: 20-Jan-2006   VLM: 324 Main Features IEEE 802.3-2002 compliant Supports only full duplex operations Supports full duplex flow control FCS generation for transmit, check for receiving packets. GMII interface to PHY layer and Simple application interface. Simple Ho...   Category :: Communication controller Language :: Verilog Development status :: Planning   10G Ethernet MAC   Updated on: 10-Apr-2008   VLM: 423 The 10G ethernet mac core. It is compliant with ieee 802.3ae. Transmit engine and Receive engine have been finished.   Category :: Communication controller Language :: Verilog Development status :: Alpha   10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Aug-2008   VLM: 1785 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   8b10b Encoder/Decoder   Updated on: 05-Oct-2006   VLM: 495 This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limit...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   a VHDL 16550 UART core   Updated on: 22-Jul-2008   VLM: 867 a 16550 compatible UART in VHDL   Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable   A VHDL CAN Protocol Controller   Updated on: 03-Nov-2007   VLM: 494 A VHDL translation of the Verilog CAN Protocol Controller   Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Production/Stable   Adaptive LMS equalizer   Updated on: 25-Apr-2006   VLM: 271 This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller Category :: DSP core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Beta   adat receiver   Updated on: 25-Jul-2008   VLM: 311 This is a feed forward receiver for an 8 channel ADAT lightpipe optical audio datastream. It outputs the audio data on a data bus, user databits on seperate pins, each updated every ADAT frame. It also outputs the recovered wordclock on a pin. ...   Category :: Communication controller Language :: VHDL Development status :: Alpha   AMI / HDB1 Line Codes   Updated on: 25-Nov-2007   VLM: 113 VHDL implementation of the AMI --- Alternate Mark Inverse --- and HDB1 --- High Density Bipolar of Order 1 line codes. For HDBn of higher order look at: http://www.opencores.org/projects/hdbn   Category :: Communication controller Language :: VHDL Development status :: Production/Stable   Automatic BAUD rate generator   Updated on: 21-Jan-2007   VLM: 183 This module allows for RS232 serial communications (UART) to automatically synthesize a BAUD rate to match incoming serial data, regardless of the FPGA clock rate. It works by measuring the speed of the incoming characters, and producing its own...   Category :: Communication controller Development status :: Production/Stable   baud generator   Updated on: 20-Dec-2007   VLM: 209 block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse. Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Param...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Bluespec 802.11a Transmitter   Updated on: 02-Jul-2008   VLM: 243 This Project is the implementation of a 80.211a Transmitter baseband block in BSV (Bluespec SystemVerilog).   Category :: Communication controller Language :: Other Development status :: Production/Stable   Bluetooth baseband controller   Updated on: 16-Mar-2002   VLM: 397 The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Alpha   CAN Protocol Controller   Updated on: 30-Apr-2008   VLM: 1515 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   E1 Framer/Deframer   Updated on: 04-May-2007   VLM: 224 CCITT G.704,G.706 E1 framer for 30 64kbps voice/data channel framing at 2.048 MHz bit rate.   Category :: Communication controller Language :: VHDL Development status :: Planning   E1-G.703,G.704,G.706 framer/deframer   Updated on: 03-Jul-2002   VLM: 181 Part of E1 equipment. May be used in E1 MUX and other communication devices with E1 port.   Category :: Communication controller Development status :: Beta   EBU/spdif to I2S project   Updated on: 29-Nov-2004   VLM: 200 this program in vhdl decodes an EBU/SPDIF input and transforms it to I2s ,   Category :: Communication controller Language :: VHDL Phaze :: Design done   EPP v1.9   Updated on: 27-Apr-2003   VLM: 126 well It will be a simple EPP interface from a prepherial point of view , and will be a FSM based synchronous design in verilog.   Category :: Communication controller Development status :: Mature   Ethernet 10GE MAC   Updated on: 07-Jun-2008   VLM: 330 The 10GE MAC implements the MAC layer for 10Gbps operation as defined in 802.3ae. The MAC is designed to be compact while providing the necessary functionally to be compliant.   Category :: Communication controller Language :: SystemC Language :: Verilog License :: LGPL Standard :: Wishbone compliant core Development status :: Beta   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   VLM: 4258 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   FireWire (IEEE 1394)   Updated on: 17-Feb-2003   VLM: 274 FireWire, an Apple trademarked name for IEEE 1394 protocol, is a high performance serial bus protocol to provide easy-to-use, low-cost, high-speed communications   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Planning   Gamepads   Updated on: 15-Sep-2005   VLM: 256 A collection of cores that interface to various gamepads.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   General-Purpose I/O (GPIO) Core   Updated on: 16-Jul-2004   VLM: 318 The GPIO IP core is user-programmable general-purpose I/O controller.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   HDB3/B3ZS Encoder+Decoder   Updated on: 16-Mar-2006   VLM: 209 HDB3/HDB2/B3ZS Encoder+Decoder cores   Category :: Communication controller Language :: VHDL Development status :: Production/Stable   HDLC controller   Updated on: 14-Nov-2001   VLM: 423 8 bit parallel backend interface, uses external RX and TX clocks.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   HyperTransport Tunnel   Updated on: 23-May-2006   VLM: 173 A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel has two HT ports to allow it to be used inside a chain of components.   Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Beta   I2C controller core   Updated on: 09-Aug-2008   VLM: 3011 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C master/slave Core   Updated on: 27-Jun-2008   VLM: 753 The design is capable of working as both I2C compatible master and slave.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   I2C Traffic Logger   Updated on: 10-May-2004   VLM: 218 An I2C 2 wire serial bus logger designed on Verilog synthesized code captures I2C transections into an external memory. The size of the transection captured is limited by the size of the external memory. I2C traffic logger is an essential di...   Category :: Communication controller Development status :: Mature   I2S Interface   Updated on: 02-Feb-2008   VLM: 777 The I2S bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between a cpu/dsp and a DAC/ADC. This core implements I2S transmitter and receiver.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2S to Paralell ADC/DAC controller   Updated on: 20-Dec-2005   VLM: 231 This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2C (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   IrDA   Updated on: 26-Aug-2002   VLM: 241 WISHBONE-compatible IrDA communication controller.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   LPC ROM emulator on USB dongle FPGA core set   Updated on: 21-Jul-2008   VLM: 475 This is ROM emulator/debugger hardware project in a USB dongle board format containing: Cyclone FPGA EP1C6T144C8N Serial Platform Flash Intel Strata Flash E28F128 (16MB) in 16 bit mode FTDI parallel to USB bridge FT245BM 4 segment LED displ...   Category :: Prototype board Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 27-Aug-2008   VLM: 635 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Manchester to UART converter   Updated on: 24-Nov-2004   VLM: 230 Bi-phase signal in Bosch Manchester Format send from Bosch control Keyboard Convert to UART signal.   Category :: Communication controller Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   MOST Network Interface Controller   Updated on: 25-Dec-2005   VLM: 177 Media Oriented Systems Transport is a multimedia fiber-optic network optimized for automotive applications. It is a network developed by the automotive industry for the automotive industry. Its design allows it to provide a low-overhead and low-c...   Category :: Communication controller Dependencies :: Technology Language :: Verilog Development status :: Planning   OFDM modem   Updated on: 19-Apr-2006   VLM: 360 A OFDM modem is the base for the DMT modulation and the 802.g.   Category :: Communication controller Language :: VHDL Development status :: Beta   OFDM modulator   Updated on: 15-Jul-2007   VLM: 327 OFDM modulator according to 802.11a standard. This model is describe in SystemC language.   Category :: Communication controller Language :: SystemC Development status :: Planning   OPB SPI Slave   Updated on: 15-May-2008   VLM: 266 The OPB SPI-Slave Core is full configurable and support DMA-Transfers to write or read data directly to a memory. The SPI-Slave receive/transmit Data to a SPI-Master, for example a DSP or processor. The SPI-Clock and OPB-Bus clocks are complete...   Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   OPB-compatible OneWire Master   Updated on: 09-Oct-2007   VLM: 142 This is a OneWire Master core that is fully compatible with the Xilinx OPB specification.   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   PS2 Core   Updated on: 30-Oct-2003   VLM: 264 This is a generic PS/2 UART for adding mice and keyboard to your projects.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Beta   Quadrature Decoder / Counter   Updated on: 23-Apr-2004   VLM: 334 Many devices use a process called quadrature to encode movement information. Use of two logic inputs can specify both direction and movement information reliably. This project is intended to provide a quick solution to those wishing to keep tra...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Reverse CDMA Access Channel Controller   Updated on: 06-Jun-2006   VLM: 138 This project is aimed at designing a Digital Architecture for Reverse CDMA Access channel and Implement it VHDL Download the source and Report Here http://www.geocities.com/deepucjohn/source.zip   Category :: Communication controller Development status :: Production/Stable   SD/MMC Bootloader   Updated on: 18-Aug-2007   VLM: 684 Small CPLD design to configure and bootstrap FPGAs from SD and MMC cards in SPI mode.   Category :: Prototype board Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   SD/MMC Controller   Updated on: 25-Aug-2008   VLM: 1206 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Serial UART   Updated on: 22-Jan-2004   VLM: 959 Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost...   Category :: Communication controller Development status :: Production/Stable   Serial Uart   Updated on: 21-Jan-2003   VLM: 527 An other version of a tiny Uart. designed to fit in a small FPGA.   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Mature   Simple Asynchronous Serial Controller   Updated on: 30-Mar-2006   VLM: 394 Simple asynchronous serial controller with flow control   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   Single Slot PCM Interface   Updated on: 10-Feb-2004   VLM: 221 Single Slot (Channel) PCM interface enables to exchange of PCM data with many popular devices (e.g. any TI DSP). This controller support 16 bit data, and allows the user to adjust the start of the bit stream.   Category :: Communication controller Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   Smartcard interface (ISO7816-3)   Updated on: 26-Oct-2006   VLM: 243 Basic functionality for implementing a Smartcard. Sends and receives bytes. Sends an ATR (Answer to Reset) on reset. Interfaces with a layer that knows how to interpret commands via a Wishbone interface.   Category :: Communication controller Development status :: Planning   smbus_if   Updated on: 22-Jan-2004   VLM: 138 The System Management Bus (SMBus) is a two-wire interface through which simple system and power management related chips can communicate with the rest of a system. SMBus provides a control bus for system and power management related tasks. The SM...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Planning